1. Technical Field
The present invention relates to semiconductor interconnect structures and fabrication methods, and in particular to shaped interconnect structures made by image reversal patterning.
2. Description of the Related Art
The speed of propagation of interconnect signals is an important factor controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area and number of interconnect levels are increased. Throughout the semiconductor industry, there has been a strong drive to reduce the dielectric constant, k, of the interlayer dielectric (ILD) materials used to electrically insulate metal lines. As a result, interconnect signals travel faster through conductors due to a reduction in resistance-capacitance (RC) delays.
Semiconductor chips may employ copper (Cu) as the electrical conductor inorganic organosilicates as the low dielectric constant (low-k) dielectric, and multiple levels of Cu/low-k interconnect layers. These Cu/low-k interconnect layers are fabricated with an iterative additive process, called dual-damascene, which includes several processing steps including, for example, film deposition, patterning by lithography and reactive ion etching, liner (Cu barrier) deposition, Cu metal fill by electrochemical plating, and chemical-mechanical polishing of excessive Cu metal.
Traditional dual-damascene integration suffers from poor reliability, particularly in porous low-k dielectric material. While hardmask layers may serve to protect the low-k material, the presence of sacrificial hardmask layers adds enormous process complexity and manufacturing as additional film deposition, pattern transfer etch, and removal of the hardmask layers are needed. Even with a hardmask, the process induced dielectric damage on the top surface of the dielectric results in a dielectric breakdown at this region during electrical reliability tests. The processes that could induce dielectric damage include chemical mechanical polishing, cleaning, and reactive ion etching.
A back-end-of-the-line (BEOL) integration process, called a low temperature oxide (LTO) process, employs a plurality of layers (e.g., up to 8) of sacrificial hardmask materials to fabricate a two-layer dual-damascene interconnect structure. Although immensely popular in semiconductor manufacturing, the dual-damascene integration scheme suffers from several drawbacks including the following. The dual-damascene integration scheme constitutes a significant portion of manufacturing cost of advanced semiconductor chips as many layers are needed to form connections. The dual-damascene integration scheme is a main yield detractor as the many layers of films needed to form the interconnects generates opportunities for defect introduction and, thus, degrade manufacturing yields. The dual damascene integration is very inefficient and embodies enormous complexity. The current dual-damascene integration scheme requires many sacrificial films (e.g., 80% of the film stack) to pattern and protect the fragile interlayer dielectric films from damage during processing. These sacrificial patterning and protective films have to be removed after patterning and copper plating.
In addition, the performance gain by introduction of new lower-k materials is often offset by the need for higher-k non-sacrificial protective materials, such as a cap layer, a hardmask layer, or a thicker copper barrier layer. The complex dual-damascene process lengthens manufacturing turn-around time and development cycles. Plasma etching processes for the dual-damascene integration scheme are also expensive and require significant up-front capital investment. The process induced dielectric damage can cause degradation in performance and reliability of the resultant chips.